研究方向

1.    人工神经形态器件与类脑计算(Artificial Neuromorphic Devices and Brain-Inspired Computing


    图片2.png

研究内容简介


基于金属氧化物这一具有复杂的离子动力学、热和电效应及耦合作用丰富的材料体系,本课题组研制出了多款人工神经形态器件,能够高效地完成各种仿生任务以及类脑计算。通过对阻变材料中各种组分占比以及器件几何结构的精心设计,我们能够在小尺度纳米器件里实现多种复杂生物神经系统行为,目前已经设计制造并通过功能验证的器件包括:具有泄漏、累积和发放等行为的NbOx神经元;同时具有长短时程可塑性的ZnO-EMIM人工树突器件;基于YSZ的星型胶质细胞器件;功耗仅为30fJ/spike的超低功耗人工突触器件。基于这些新型神经形态器件,课题组进一步实现了包括时间序列分析、联想记忆等复杂的生物神经功能。与此方向相关的研究成果多次在领域顶级期刊上如 Nature Communications, Advanced Materials等发表。

Based on metal oxides, a material system rich in complex ionic dynamics, thermal and electrical effects and coupling effects, our group has developed a variety of artificial neuromorphic devices, which can efficiently complete various bionic tasks and brain-like computing. Through careful design of the proportions of various components in the resistive materials and the geometry of the device, we can realize a variety of complex biological nervous system behaviors in small-scale nanodevices. The devices that have been designed, manufactured and functionally verified include: NbOx neurons with behaviors such as leakage, accumulation and firing; ZnO-EMIM artificial dendritic devices with long- and short-term plasticity at the same time; YSZ-based astrocyte devices; ultra-low-power artificial devices with power consumption of only 30fJ/spike synaptic device. Based on these novel neuromorphic devices, our group has further realized complex biological neural functions including time series analysis, associative memory and so on. Research results related to this direction have been published many times in top journals in the field, such as Nature Communications, Advanced Materials, etc.



2.    基于忆阻器的高效类脑计算系统(Memristor-Based Efficient Computing System


图片1.png

研究内容简介


针对人工智能算法中计算方式的多样性,本课题组将忆阻器内部动力学特性和忆阻器阵列在存内计算方面的优势有机结合,高效地实现了包括矩阵向量乘法、衰减运算以及随机数生成在内的多种在传统计算平台中代价高昂的运算,进而在多种不同类型的人工智能硬件计算系统中达到了极低的功耗。目前代表性的系统主要包括:基于二维铁电材料α-In2Se3的短时程可塑性实现的储备池计算系统,该系统能够以极低的功耗有效地处理复杂的时序信息;基于相变存储器 PCM 电导漂移行为的资格迹计算系统,该系统能够利用PCM电导漂移导致的衰减高效地实现资格迹机制并能有效加速强化学习的训练过程;基于TaOx长时程可塑性的优化问题求解系统等。该方向的研究成果多次发表在如 Science Advances, Advanced Materials, IEDM 等微电子领域内顶级期刊和杂志中。

In view of the diversity of computing methods in artificial intelligence algorithms, our group combines the internal dynamic characteristics of memristors with the advantages of memristor arrays in in-memory computing, and efficiently implements a variety of expensive operations in traditional computing platforms, including random number generation, matrix-vector multiplication, matrix attenuation and so on. As a result, we have achieved extremely low power consumption in many different types of artificial intelligence hardware computing systems. The current representative systems mainly include: the reservoir computing system based on the short-term plasticity of the two-dimensional ferroelectric material α-In2Se3, which can efficiently process complex timing information with extremely low power consumption; the phase-change memory(PCM)-based eligibility trace calculation system, which can efficiently implement the eligibility trace mechanism by using the attenuation caused by PCM conductance drift and can effectively accelerate the training process of reinforcement learning; the optimization problem solving system based on long-term plasticity TaOx memristor, etc. The research results in this direction have been published many times in top journals and conferences in the field of microelectronics such as Science Advances, Advanced Materials, IEDM, etc.




3.    面向人工智能的类脑芯片设计与制造(Design and Manufacture of Memristor Chips for Artificial Intelligence


图片3.png

研究内容简介


针对高能效神经网络处理硬件,本课题组研究了面向存内计算的高性能阻性存储器集成工艺、多值存储器件、高效读写和计算电路以及系统级芯片架构等,重点解决器件性能优化和先进工艺集成、模数接口电路设计与软硬件协同设计等存内计算架构中的关键问题。

For high-efficiency neural network processing hardware, our group has studied high-performance resistive memory integration technology for in-memory computing, multi-value storage devices, efficient read-write and computing circuits, and system-level chip architecture, focusing on device performance optimization and Key issues in in-memory computing architecture, such as advanced process integration, analog-digital interface circuit design, and software-hardware co-design.



4.    面向人工智能的忆阻存算一体化芯片设计与制造(Design Fabrication of Memristor-Based Compute-in-Memory Chips for Artificial Intelligence

微信图片_20230918152147.png


随着人工智能的飞速发展,以深度学习为代表的先进算法模型的参数量和计算量逐年激增,这对以冯诺依曼架构为主的传统计算硬件平台提出了新的挑战。本课题组聚焦边缘端智能应用和云端大数据应用所面临的大算力及高能效需求,研究面向忆阻存算一体化芯片的高效存储器电路设计、高性能模数转换电路设计、先进算子加速核心设计、多核心片上网络架构设计,先进算法模型压缩和本地高效部署。课题组与代工厂长期保持紧密合作,该方向的研究成果已发表在诸如JSSCTCAS-I等芯片设计领域顶级期刊中。

With the rapid development of artificial intelligence, the number of parameters and computation of advanced algorithmic models represented by deep learning is surging year by year, which poses a new challenge to the traditional computing hardware platforms based on the von Neumann architecture. Focusing on the need for big computing power and high energy efficiency in intelligent applications at the edge and big data applications in the cloud, our group is committed to the study on design of high-efficiency memory circuits, high-performance analog-to-digital converter circuits, advanced operator accelerators, multi-core network-on-chip architectures, compression and local efficient deployment of advanced algorithmic models with respect to the memristor-based compute-in-memory chips for artificial intelligence. We have been working closely with foundries for a long time, and the research results have been published in the top journals in the field of chip design, such as JSSC and TCAS-I.



5.    高通量低功耗脑机接口解码芯片与技术(High-Throughput Low-Power Brain-Machine Interface Decoding Chip and Technology


图片4.jpg

研究内容简介


研究团队致力于研发大算力、高能效的脑机解码芯片与应用系统,利用新型非易失性忆阻器件及其嵌入式芯片制造核心制备流程与工艺,探索面向脑机解码算法的新电路、新架构、新映射方案、新调度流程等,突破忆阻器芯片解码脑机信号(例如EEG、ECoG等)的技术难题。本研究将重点对典型脑机算法进行软硬件协同设计,提出新的网络重构、量化压缩、并行处理等优化方案,着重解决当前脑机算法难以扩展到忆阻器硬件进行存算一体化运行的核心问题,实现忆阻器脑机解码的异构集成芯片及其FPGA系统构建与演示,在同等算力下相比于传统冯诺依曼架构芯片方案可在能效上达到数量级的提升,真正满足脑机应用场景高实时性、极低功耗等未来需求。

Our team is dedicated to developing high-performance and energy-efficient brain-machine decoding chips and application systems. Leveraging the core preparation processes and technologies of novel non-volatile resistive memory devices and their embedded chip manufacturing, we proactively explore new circuits, architectures, mapping schemes, and scheduling processes tailored for brain-machine decoding algorithms, aiming to overcome technical challenges in decoding brain-machine signals (such as EEG, ECoG, etc.) using resistive memory chips.This research focuses on proposing new network reconstruction, quantization compression, parallel processing and other optimization solutions for the hardware and software co-design of typical brain-machine algorithms. We aim to address the core issue that it is difficult to extend the current brain-computer algorithm to the memristor hardware for integrated operation of storage and computation. We aim to realize heterogeneous integrated chips for resistive memory-based brain-machine decoding, along with the construction and demonstration of FPGA systems. Compared to traditional von Neumann architecture chip solutions, our approach can achieve a significant improvement in energy efficiency under equivalent computing power, truly meeting the future demands of high real-time performance and ultra-low power consumption in brain-machine application scenarios.





TOP